Field-effect transistor and manufacture thereof

ABSTRACT

A source and a drain of a field-effect transistor are formed so as to fulfill a specified physical relationship to upper and lower gates thereof and thereby parasitic capacitance that hampers its high-speed operation is minimized. The filed-effect transistor includes a second support substrate, a lower gate that is embedded in an insulator formed on the second support substrate, an insulating layer formed on the lower gate, a semiconductor layer formed on the insulating layer, an insulating layer formed on the semiconductor layer, an upper gate formed on the insulating layer, as well as a source electrode, a drain electrode, an upper gate electrode, and a lower gate electrode all of which are isolated from one another by the insulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is divisional of U.S. patent application Ser.No. 09/750,441, filed Dec. 28, 2000, which claims priority to JapanesePatent Application No. 2000-020045, filed Jan. 28, 2000, the content ofwhich are incorporated hereinto by reference.

BACKGROUND OF THE INVENTION

[0002] 1. The Field of the Invention

[0003] The present invention relates to a method for forming an embeddedgate to realize a high-performance transistor, and particularly to adouble-gate field-effect transistor that is obtained by forming finegates, and a method for manufacturing the same.

[0004] 2. The Relevant Technology

[0005] In connection with a progress of transistors towardminiaturization, a short channel effect that the threshold voltage ofthe transistor varies due to variation in the gate length of thetransistor becomes significant. To prevent the short channel effect andincrease driving capability of the transistor, it is known that the useof the double gate structure in the transistor (refer to Japanese PatentApplication Laid-open No. 62-1270 (1987)) is the most suitable method.

[0006] However, up to the present, there has not been known anindustrial method for manufacturing the double gate structurepractically. Especially, a method for manufacturing the double gate insuch a way that a source and a drain are formed so as to fulfill aspecified physical relationship to the upper and lower gates forminimizing parasitic capacitance that hampers a high-speed operationthereof is not yet in sight in every way.

BRIEF SUMMARY OF THE INVENTION

[0007] The present invention was devised with intent to solve theabove-mentioned problem, and the object of the present invention is toprovide a double-gate field-effect transistor with aligned upper andlower gates, and an industrial method for manufacturing the same.

[0008] The present invention is devised to achieve such objects asmentioned above, and a first invention as included by the presentinvention has a transistor structure comprising: a first gate embeddedin an insulator on a support substrate and being in contact with aninsulating layer on the insulator; a source and a drain formed in asemiconductor layer on the insulating layer; and a second gate formed inan embedded insulating layer that is formed on the semiconductor layer,and is characterized in that the first gate and the second gate areopposite to each other through the intermediaries therebetweenconsisting of the insulating layer, the semiconductor layer, and theembedded insulating layer.

[0009] Furthermore, a second invention as included by the presentinvention is characterized in that wiring of four electrodes that are tobe connected to the source, the drain, the first gate, and the secondgate, respectively, is formed in the first invention.

[0010] Moreover, a third invention as included by the present inventionis characterized in that an adjustment hole that reaches as deep as thesupport substrate is provided in a depressed manner to position thefirst gate and the second gate to each other in the first invention.

[0011] Furthermore, a fourth invention as included by the presentinvention is characterized by comprising the steps of: forming asemiconductor layer on a first support substrate through theintermediary of an embedded insulating layer; forming an adjustment holethat penetrates the embedded insulating layer and the semiconductorlayer in a depressed manner on the first support substrate; providingfurther an insulating layer on the semiconductor layer and forming afirst gate at a predetermined position set apart from the adjustmenthole on the insulating layer; forming the insulator on the insulatinglayer and further gluing a second support substrate onto the insulator;removing the first support substrate and forming a second gate at apredetermined position set apart from the adjustment hole on theembedded insulating layer; and providing a source and a drain on theembedded insulating layer side and forming wiring of electrodes thatconnects to the source, the drain, the first gate, and the second gate,respectively.

[0012] According to the present invention that specifies suchconfiguration as this, a method for manufacturing easily a double-gatefiled-effect transistor with aligned upper and lower gates of a finestructure capable of high-speed operation can be provided.

[0013] The above and other objects, features and advantages of thepresent invention will become more apparent from the followingdescription of embodiments thereof taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a structural drawing showing an example of an SOIsubstrate;

[0015]FIG. 2 is a structural drawing showing an example of a procedurefor isolating regions in the method for manufacturing a field-effecttransistor according to the present invention;

[0016]FIG. 3 is a structural drawing showing an example of a firstsupport substrate on which an adjustment mark is formed in the methodfor manufacturing the field-effect transistor according to the presentinvention;

[0017]FIG. 4 is a structural drawing showing one example of a procedurefor making a lower gate in the method for manufacturing the field-effecttransistor according to the present invention;

[0018]FIG. 5 is a structural drawing showing how a lamination agent isformed in the method for manufacturing the field-effect transistoraccording to the present invention;

[0019]FIG. 6 is a structural drawing showing a situation where a secondsupport substrate is glued to the first support substrate in the methodfor manufacturing the field-effect transistor according to the presentinvention;

[0020]FIG. 7 is a structural drawing showing a situation where the firstsupport substrate is removed in the method for manufacturing thefield-effect transistor according to the present invention;

[0021]FIG. 8 is a structural drawing showing one example of a procedurefor making an upper gate in the method for manufacturing thefield-effect transistor according to the present invention; and

[0022]FIG. 9 is a structural drawing showing one example of a procedurefor making electrodes in the method for manufacturing the field-effecttransistor according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] A form of implementing a field-effect transistor according to thepresent invention is described referring to the drawings based on oneembodiment. The method for manufacturing a double-gate field-effecttransistor with aligned upper and lower gates according to the presentinvention will be explained step by step in FIGS. 1 to 9.

[0024] First, explained is one example of a manufacturing process of afirst support substrate in the method for manufacturing a field-effecttransistor according to the present invention. FIG. 1 shows one exampleof an SOI (SILICON ON INSULATOR) substrate. The SOI substrate is suchthat an embedded insulating layer 11 is formed on the first supportsubstrate 10 and further a semiconductor layer 12 (for example, a thinsilicon film) is formed thereon.

[0025]FIG. 2 shows one example of a procedure of region isolation. Apart of both of the embedded insulating layer 11 and the semiconductorlayer 12 on the first support substrate 10 is removed using alithography technique and an etching technique and an insulating layer21 is formed on this region. A region of the insulating layer 21 isnamed as an adjustment mark region B and an adjustment mark is formed inthis region. Thus, a device region A and the adjustment mark region Bare formed on the support substrate.

[0026]FIG. 3 shows one example of the first support substrate on whichthe adjustment mark was formed. An adjustment mark C is formed bydigging a groove in the adjustment mark region B by etching. The depthof the groove goes down to reach the first support substrate 10 and thisdepth is such a depth that enables to recognize the adjustment mark Cfrom the back side when the first support substrate 10 is removed in asubsequent process.

[0027] Next, explained is one example of a process of gluing the firstsupport substrate and the second support substrate together in themethod for manufacturing the field-effect transistor according to thepresent invention. FIG. 4 shows one example of a procedure for making alower gate. A gate layer is formed on an insulating film 40 on thesemiconductor layer 12 in the device region A. Next, the gate layer isprocessed by etching to form a lower gate 41 which is a first gate so asto fulfill a specified physical relationship to the adjustment mark C.

[0028]FIG. 5 shows a situation where a lamination agent is formed. Afterthe formation of the lower gate 41, lamination agents (insulators) 50 ato 50 d for gluing the second support substrate to this structure on thefirst support substrate are formed. Therefore, the lower gate 41 isembedded in the lamination agent (insulator) 50 a.

[0029]FIG. 6 shows a situation where the second support substrate isglued to the first support substrate. The first support substrate 10 andthe structure constructed thereon in which the lower gate 41 was formedare reversed upside down and glued to a second support substrate 60 thatwas prepared separately.

[0030] Next, explained is one example of the manufacturing process ofthe second support substrate in the method for manufacturing thefield-effect transistor according to the present invention. FIG. 7 showsa situation where the first support substrate is removed. The firstsupport substrate 10 is removed by etching, using the embeddedinsulating layer 11 as a removal stop layer. On this occasion, thelamination agent insulator) 50 c that was formed inside the adjustmentmark C is exposed.

[0031]FIG. 8 shows one example of a procedure for making an upper gate.The embedded insulating layer 11 is selectively removed by etching, andsubsequently a gate layer is formed. The gate layer is processed byetching and an upper gate 81 which is the second gate is formed. Theformation of the upper gate 81 is fabricated by etching the gate layerwhile a position of the upper gate 81 is aligned to the lower gate 41through the use of the adjustment mark C that was exposed. Through thesesteps, the upper gate 81 (the second gate) and the lower gate 41 (thefirst gate) can be aligned to each other.

[0032]FIG. 9 shows one example of a procedure for making electrodes.Interlayer insulating films 90 a to 90 c are formed at the side of theremoved first support substrate 10 and subsequently a source electrode91 and a drain electrode 92 are formed. Moreover, an upper gateelectrode 93 connecting to the upper gate 81 and a lower gate electrodeconnecting to the lower gate 41 are formed. Incidentally, the lower gateelectrode connecting to the lower gate 41 is not shown in the figure.The lower gate electrode is connected to the lower gate 41 by digging ahole for contact through the interlayer insulating film in a regionother than the device region A, either in a region located in thebackward region or in a region located in the frontward region. In thisway, there can be obtained the double-gate field-effect transistor withaligned upper and lower gates having four electrodes wherein the sourceelectrode 91, the drain electrode 92, the upper gate electrode 93, andthe lower gate electrode are positioned on the side of the first supportsubstrate 10 that has been removed.

[0033] The double-gate field-effect transistor formed by theabove-described manufacturing method includes the second supportsubstrate, the lower gate embedded in the insulator formed on the secondsupport substrate, the insulating layer formed on the lower gate, thesemiconductor layer formed on the insulating layer, a source and a drainformed in the semiconductor layer, the insulating layer formed on thesemiconductor layer, the upper gate formed on the insulating layer, aswell as the source electrode, the drain electrode, the upper gateelectrode, and the lower gate electrode.

[0034] The present invention has been described in detail with respectto preferred embodiments, and it will now be apparent from the foregoingto those skilled in the art that changes and modifications may be madewithout departing from the invention in its broader aspect, and it isthe intention, therefore, in the apparent claims to cover all suchchanges and modifications as fall within the true spirit of theinvention.

What is claimed is:
 1. A double-gate field-effect transistor having astructure that comprises: a first gate that is embedded in an insulatoron a support substrate and contacts with an insulating layer on saidinsulator; a source and a drain formed on a semiconductor layer on saidinsulating layer; and a second gate that is formed on an embeddedinsulating layer formed on said semiconductor layer, wherein said firstgate and said second gate are opposite to each other through theintermediaries of said insulating layer, said semiconductor layer, andsaid embedded insulating layer.
 2. A double-gate field-effect transistoraccording to claim 1, wherein wiring of four electrodes that are eachconnected to said source, said drain, said first gate, and said secondgate is formed.
 3. A double-gate field-effect transistor according toclaim 1, wherein an adjustment hole that reaches as deep as said supportsubstrate is provided in a depressed manner in order to position saidfirst gate and said second gate to each other.